The present invention relates to a plasma processing apparatus and a plasma processing method. The plasma processing apparatus includes a processing chamber in a vacuum chamber and a sample stage disposed within the processing chamber to mount a substrate-shaped sample, such as a semiconductor wafer, on a top surface thereof. In the plasma processing apparatus, the sample is processed by using plasma formed in the processing chamber. The present invention relates to a plasma processing apparatus or a plasma processing method in which processing of the sample is executed by supplying radio frequency (RF) power to an electrode disposed within the sample stage while forming plasma.
In the manufacture process of semiconductor devices, etching processing of the sample using the above-described plasma processing apparatus, i.e., the so-called dry etching is generally conducted. As for the plasma processing apparatus for conducting such etching, various systems are used. Formerly, such a plasma processing apparatus includes a processing chamber, a gas supply apparatus, a vacuum pumping apparatus, a lower electrode, and a plasma generation unit. The processing chamber is a space disposed within the vacuum chamber to conduct processing. The gas supply apparatus includes a path connected to the vacuum chamber and communicated with inside of the processing chamber to supply process gas to the processing chamber. The vacuum pumping apparatus includes a vacuum pump, such as a turbo-molecular pump, to decompress the inside of the processing chamber and adjust the pressure to a value in a desired range suitable for processing. The lower electrode is a sample stage. A substrate-shaped sample, such as a semiconductor wafer, is mounted on a dielectric film disposed on the sample stage. The plasma generation unit includes a means for generating an electric field (EF) and a magnetic field supplied to generate plasma in the processing chamber.
A sample is mounted on the top surface of the sample stage. In this state, process gas is supplied into the processing chamber from a gas supply opening, such as a shower plate, which forms a ceiling of the processing chamber. The electric field or the magnetic field supplied by the generation means excites the process gas and brings about a plasma state. As a result, plasma is formed in a space over the sample stage in the processing chamber. In this state, a disk or cylindrical shaped electrode made of metal disposed within the sample state and connected electrically to a radio frequency power supply is supplied with radio frequency (RF) power. Consequently, a bias potential depending upon potential of plasma is formed over the sample. As a result, charged particles in the plasma are attracted to the top surface of the sample to collide with the top surface. In this way, etching processing of a film structure including a mask and a film layer to be processed, disposed on the top surface of the sample previously is started.
In the semiconductor manufacture process in recent years, a limit of size shrinking using optical lithography has been approached. Processes such as multiple exposure or spacer patterning are becoming the mainstream. In such multiple exposure and the spacer patterning process represented by SADP (Self Aligned Double Patterning), the etching processes increase.
Slight uniformity lowering of etching performance caused in the wafer surface in respective etching processes is accumulated by increase of etching processes. As the number of processes increases, it becomes difficult to allow even slight uniformity lowering in the wafer surface. In the semiconductor manufacture process represented by leading edge logic, especially in the FEOL (Front End Of Line) process, therefore, high precision control of the uniformity in the wafer surface of the etching performance is demanded. Specifically, controllability having a high degree of freedom in etching depth in the wafer surface, CD distribution control, and control from convex distribution to concave distribution is needed.
For example, in the etching process of an SIN film, etching is hampered by high concentration byproducts distributing in a central part of a wafer. In some cases, the etching rate becomes low in the central part of the wafer and the etching rate becomes high in a peripheral part of the wafer. As a result, the etching rate in the wafer surface becomes concave distribution in the radius direction. In the etching process of a poly-Si film and so forth, the plasma density becomes the highest near the center of a reactor, and becomes gradually lower as the position approaches an inner wall of the reactor. Because of such uneven distribution, the etching rate becomes high in the center part of the wafer and the etching rate becomes low in the peripheral part of the wafer. As a result, the etching rate in the wafer surface becomes convex distribution in the radius direction in some cases.
In order to solve such insufficient uniformity of the etching rate in the wafer surface, formerly etching rate uniformalizing has been conducted by condition retrieval and condition optimization of etching recipe such as the kind and pressure of process gas. This poses a problem such as increase of the number of times of evaluation attendant upon the condition retrieval and consequent increase in time and cost.
If parameters such as radio frequency power for generating plasma and a magnetic field condition for controlling plasma distribution are changed to change plasma characteristics, not only plasma distribution but also plasma characteristics, especially the radical density and distribution, plasma density and distribution, and wafer temperature attendant upon a change of ion quantity change simultaneously. In this way, complicated correlations among mutual parameters exist. In the convention apparatuses, therefore, it becomes often difficult to conduct process construction that reconciles the etching material selectivity and the etching rate uniformity.
As a technique for improving the unifoimity of the etching rate against such a problem, a technique disclosed in JP-A-2008-244063 is formerly known. With respect to the top surface direction of a sample stage mounting a wafer, which is a sample, magnitude of a current of RF power (RF biasing power) for forming a bias in the wafer surface is adjusted by using variable impedances connected between a plurality of divided electrodes and an RF biasing power supply. It is stated in JP-A-2008-244063 that uniformity of etching is implemented by adjusting the magnitude of the current of RF power.
Furthermore, JP-A-2002-141340 and JP-A-2001-319920 also disclose a technique of adjusting a current of a radio frequency for forming bias potential with respect to the inside of the wafer surface or the top surface direction of the lower electrode. In JP-A-2002-141340, an electrode is disposed within a sample stage on a periphery side of a sample mounting surface to surround the sample mounting surface. A bias current is leaked from an RF biasing power supply to the electrode via a variable impedance element. As a result, occurrence of charging damage on the sample due to charged particles, such as electrons, in plasma attracted by bias potential is suppressed. In this way, the yield is prevented from lowering. In JPA-2001-319920, the lower electrode is disposed to be divided into a plurality of sections in a radius direction of a mounting surface. Respective sections are connected to a biasing power supply circuit having a variable impedance element thereon. In such a configuration, the variable impedance value is adjusted to make ion energy incident on a wafer, which is a sample, uniform in an in-surface direction. In this way, it is attempted to suppress occurrence of charging damage of the wafer.